The present invention relates to the fabrication of integrated circuits. More particularly, the present invention is directed toward a method and apparatus for achieving void-free trench fill on substrates having high aspect ratio trenches.
Semiconductor device geometries continue to decrease in size, providing more devices per unit area on a fabricated wafer. These devices are initially isolated from each other as they are built into the wafer, and they are subsequently interconnected to create the specific circuit configurations desired. Currently, some devices are fabricated with feature dimensions as small as 0.08 xcexcm. For example, spacing between devices such as conductive lines or traces on a patterned wafer may be separated by 0.08 xcexcm leaving recesses or gaps of a comparable size. A nonconductive layer of dielectric material, such as silicon dioxide, is typically deposited over the features to fill the aforementioned gap and insulate the features from other features of the integrated circuit in adjacent layers or from adjacent features in the same layer.
Shallow trench isolation (xe2x80x9cSTIxe2x80x9d) is a technique for isolating devices having feature dimensions of under about 1 xcexcm. FIG. 1 shows an example of an STI trench substrate 10, such as a semiconductor wafer, having two islands 12 covered by a trench mask 13. A trench 14 is disposed between the two islands 12 which define the sidewalls 16 of the trench 14. The mask 13 is typically a patterned trench mask layer made of a relatively hard material such as silicon nitride (SiN) used in forming the trench. A thermal oxide layer (not shown) is grown on the surfaces of the trench 14. The silicon nitride mask 13 prevents oxidation of the silicon substrate 10 where active devices are to be formed, and is also referred to as the oxidation mask. The trench 14 is filled by depositing an insulating or dielectric material 18 such as silicon dioxide over the entire trench mask 13. The silicon dioxide overfills the trench 14 to create an irregular top surface topography. The excess material along with the silicon nitride mask 13 is typically removed to planarize the trench 14 so that the trench-fill material 18 is flush with the islands 12.
One gap-fill issue encountered when the feature dimensions of the integrated circuits decrease is that it becomes difficult to fill the trenches, as in the case of STI structures. This problem is referred to as the gap-fill problem and is described below in conjunction with FIGS. 1 and 2. In the vertical cross-sectional view of FIG. 1, the sidewalls 16 of the trench are formed by one edge of each of the two adjacent islands 12. During deposition, dielectric gap-flu material 18 accumulates on the surfaces 20 of the islands 12 as well as on the substrate surface, and forms overhangs 22 located at the corners 24 of the islands 12. As deposition of the gap-fill material 18 continues, the overhangs 22 typically grow together faster than the trench 14 is filled until a dielectric layer 26 is formed, creating an interior void 28, shown more clearly in FIG. 2. In this fashion, the dielectric layer 26 prevents deposition into the interior void 28. The interior void 28 can be problematic to device fabrication, operation, and reliability.
Many different techniques have been implemented to improve the gap-filling characterstics of dielectric layers, including deposition etch-back (dep-etch) techniques. One such dep-etch technique involves physical sputtering of the dielectric layer by ion bombardment to prevent the formation of voids during a deposition process. The effects of the physical sputtering dep-etch technique is shown in FIG. 3. As shown in FIG. 3, ions 30 incident on the dielectric material transfer energy thereto by collision, allowing atoms 32 to overcome local binding forces and eject therefrom. During the dep-etch technique, dielectric material fills the trench 14 forming a surface 34. The surface 34 lies in a plane that extends obliquely to the sidewalls 16, commonly referred to as a facet. This dep-etch technique may be applied sequentially so that the dielectric layer 26 is deposited and then subsequently etched followed by deposition of additional dielectric material. Alternatively, the deposition process and the etch process may occur concurrently. Whether the deposition and etching are sequential or concurrent, the first order effects on the profile of the surface of the dielectric layer 26 profile are the same.
Typically, a plasma-chemical vapor deposition (CVD) process is employed to deposit a dielectric layer using the dep-etch technique. A plasma is generated to produce chemical reactive plasma species (atoms, radicals, and ions) that are absorbed on the surface of the substrate. For example, a plasma-enhanced chemical vapor deposition (PECVD) process, including a high-density plasma-chemical vapor deposition (HDP-CVD) process (e.g., a plasma formed by applying RF power to an inductive coil or by electron cyclotron resonance chemical vapor deposition (ECR-CVD) process), may be employed. The plasma CVD processes typically allow deposition of high quality films at lower temperature and with faster deposition rates than are typically possible employing purely thermally activated CVD processes.
Referring to FIGS. 3 and 4, after an extended dep-etch technique, the portion of the dielectric layer 26 positioned adjacent to the corners 24, regardless of the spacing between the conductive features 12, has a surface 34 that forms an oblique angle with respect to the plane in which the substrate 10 lies. Thereafter, planarization may be accomplished by an extended planarization etch technique where physical sputtering is balanced with the deposition so that very narrow features become completely planarized. Alternatively, a separate planarization process may be employed that is capable of smoothing or eliminating the remaining steps of the large features.
Another gap-fill issue arises when the gap dimensions become increasingly narrow and deep so that the void 28 of FIG. 2 that can form will be deep. Such a gap is characterized by a high aspect ratio, which is defined as the depth of the gap divided by its width, of typically greater than about 3:1. It is difficult to achieve gap fill for deep voids without clipping or sputtering the silicon nitride mask 13. This clipping problem is described in connection with FIG. 5. To achieve void-free gap fill, conventional approaches decrease the deposition rate relative to the sputter rate to keep the gap open during the dep-etch process. To continue improving gap fill, lower deposition-to-sputter or deposition-to-etch (dep-etch) ratios become necessary. The lower dep-etch ratio causes the oblique facet 34 to move further apart and closer to the silicon nitride mask 13. If the dep-etch ratio is sufficiently low, the facet 34 will reach the silicon nitride mask 13 and the comers 24 of the mask 13 will be sputtered or clipped, as illustrated in FIG. 5. The clipping raises integration concerns during planarization and can lead to gate wrap around and device performance degradation.
Providing void-free gap fill is also important in processes such as the formation of inter-metal dielectric (IMD) layers, and pre-metal dielectric (PMD) layers. In an IMD process, for example, an insulating layer of typically an undoped SiO2 or fluorine-doped oxide is formed between metal interconnect layers. Although clipping of the metal interconnect layers generally does not occur, similar problems of forming a void-free gap-fill layer with superior gap-filling characteristics arise, particularly for high aspect ratio gaps.
What is needed is a method and an apparatus for depositing a gap-fill layer on a substrate with superior gap filling characteristics and little or no clipping of trench masks or other circuit elements.
The present invention provides a method and apparatus for depositing a dielectric layer employing a dep-etch technique to perform gap fill with little or no void formation and clipping. The invention achieves void-free gap fill by raising the source plasma power densities to increase the ion density and to generate a more directional deposition oriented into the gap, and by shifting the source plasma power density to concentrate a higher percentage of the power density above the gap to be filled to produce a more uniform deposition over the substrate.
The gap-fill layer is deposited employing a high-density plasma-chemical vapor deposition (RDP-CVD) system, such as an Applied Materials, Inc. Ultima HDP-CVD System Typically, a shallow trench having a high aspect ratio of about 3:1 or higher may be present on a substrate upon which the dielectric layer is to be deposited, with the substrate being positioned in a process chamber of the HDP-CVD system. Deposition gases, such as a silicon source gas and an oxygen source gas are flowed across the surface of the substrate along with an inert gas. An RF source generator and an RF bias generator are each in electrical communication with the process chamber to form a plasma from the process gas mixture (deposition and inert gases) to generate reactive plasma species for sputtering. The energy from the RF source generator is inductively coupled into the process chamber, while the energy from the RE bias generator is capacitively coupled into the process chamber.
Although sputtering can eliminate overhangs and keep the gap open during gap fill, excessive sputtering can lead to void formation by redeposition of the sputtered material The gap-fill dep-etch chemistry is preferably adjusted to control the sputter rate relative to deposition rate to reduce or eliminate void formation caused by redeposition. For instance, the amount of the inert gas component in the process gas can be adjusted to raise or lower the sputtering energy and the sputter rate and can be optimized to achieve superior gap-filling characteristics. Moreover, redeposition is less likely to occur at high temperatures because the sputtered material will tend to return to the vapor phase upon contact with a hot surface.
In accordance with an aspect of the invention, a process gas is flowed into a process chamber in a method for depositing a layer on a surface of a substrate having a trench and disposed in the process chamber. The substrate has a side edge generally surrounding the surface. The process gas includes silicon, oxygen, and an inert component. The concentration of the inert component in the process gas is less than about 40%, in volume. A plasma is formed in the process chamber to deposit the layer on the surface of the substrate and fill the trench, The formation of the plasma includes coupling source plasma energy into the process chamber at a total substrate power density of at least about 15 Watts/cm2. In one embodiment, the energy is inductively coupled into the process chamber by coupling a top RF coil at a top RF power level with a top portion of the process chamber above the surface of the substrate to produce a top power density, and coupling a side RF coil at a side RF power level with a side portion of the process chamber generally surrounding the side edge of the substrate to produce a side power density. The total power density is equal to the sum of the top power density and the side power density. The top power density and the side power density have a ratio of at least about 1.5, more desirably at least about 2. This represents a significant shift of power concentration to the top from a ratio of typically about 0.4 in previous processes. In one embodiment, the top power density is about 13.7 Watts/cm2 to about 16.9 Watts/cm2, and the side RF power density is about 4.1 Watts/cm2 to about 7.6 Watts/cm2, and the concentration of the inert component is less than about 15%, by volume. In a specific embodiment, the concentration of the inert component is about 0%.
The reduction in the concentration of inert gases may also avoid clipping during trench fill. For instance, the present invention substantially avoids sputtering the trench mask or sputters the trench mask at a substantially lower rate than the sputter rate of the trench-fill dielectric material in an STI procedure. This is accomplished by adjusting the trench-fill dep-etch chemistry, Specifically, it was discovered that the energy required to sputter the trench mask which is typically formed from silicon nitride is higher than that required to sputter the dielectric material such as silicon dioxide. The sputtering energy of the reactive plasma species varies with changes in the chemistry of the process gas mixture. The chemistry can be selected to produce predominantly plasma species that have sputtering energy sufficient to sputter the dielectric material but insufficient to cause any significant sputtering of the trench mask. For instance, it was discovered that argon ions have enough sputtering energy to sputter silicon dioxide dielectric material and silicon nitride mask, while oxygen ions have sputtering energy sufficient to sputter silicon dioxide, but cause little or no sputtering of silicon nitride. In this fashion, the sputter rate of the trench mask is substantially decreased relative to the sputter rate of the dielectric material, thereby reducing the possibility of clipping the trench mask The decreased trench mask sputter rate allows decreasing the deposition rate of the dielectric material relative to its sputter rate to achieve void-free trench fill with little or no trench mask clipping.
To further improve gap-filling characteristics, the inventors have discovered that it is advantageous to reduce or eliminate the transient effects during the initial deposition of the gap-fill layer, particularly for filling gaps with very high aspect ratios of greater than about 4:1. The transient effects produce nonuniform deposition which typically manifests itself in void formation in the gap-fill layer. The present invention reduces transient effects by introducing an inert gas into a process chamber and striking a plasma to heat the substrate to a preset temperature, which may be the temperature at which deposition is to occur. Upon reaching the preset temperature, the plasma is turned off and the process gas is flowed into the chamber without plasma excitation until the process gas flow and distribution achieve a generally steady state or equilibrium in the chamber so that the gas components of the process gas are uniformly provided to the surface of the substrate. A plasma is then formed to deposit the gap-fill layer on the surface of the substrate and fill the trench in the substrate. The preset temperature is typically about 350-450xc2x0 C. for If and about 600-760xc2x0 C. for STI, for example.